授课教师：胡昱（Bryan Yu Hu）博士，加拿大University of Alberta电子与计算机工程系助理教授

Textbooks: D. A. Patterson and J. L. Hennessy,Computer Organization and Design: The Hardware/Software Interface, 4rd Edition, Morgan Kaufmann Publishing Co., Menlo Park, CA.,. ISBN13: 978-0-12-370606-5, ISBN10: 0-12-370606-8 Paperback

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胡昱（Bryan Yu Hu）博士个人简介（http://www.ece.ualberta.ca/~bryanhu/index.html）

1. Education and Work Experience

1.1. Education

• 2005-2009 University of California Los Angeles (UCLA) Los Angeles, CA

Ph.D. in Electrical Engineering Department,

Dissertation title: Resynthesis Techniques for FPGA Optimization

• 2002-2005 Tsinghua University Beijing, China

M. Eng. in Computer Science and Technology Department

• 1998-2002 Tsinghua University Beijing, China

B. Eng. in Computer Science and Technology Department

1.2. Work Experience

• 2010/01-present University of Alberta Edmonton, AB

Assistant Professor in Electrical and Computer Engineering Department

• 2009/06-2009/12 University of California Los Angeles (UCLA) Los Angeles, CA

Post-doctoral researcher in Electrical Engineering Department

• 2005/09-2009/05 University of California Los Angeles (UCLA) Los Angeles, CA

Research assistant in Electrical Engineering Department

• 2006/06-2006/09 Research Laboratories, Xilinx Inc. San Jose, CA

Intern

• 2002/09-2005/07 Tsinghua University Beijing, China

Research assistant in EDA lab at Computer Science Department

2. Evidence of Research Impact and Contributions

• Best Paper Award Nominations

 Design Automation Conference 2010 (1%)

 International Conference on Computer-Aided Design 2009 (2%)

 International Conference on Computer-Aided Design 2008 (2%)

• Best Contribution Award at the IEEE Programming Challenge at IWLS 2008

• First place in the UCLA Knapp Venture Competition, 2009

• Honors for Graduate Research

 UCLA Dean’s Special Research Assistant Award 2007, 2008, 2009

 Outstanding Graduate Student Award from Tsinghua University, 2005 (top 2%).

• Outstanding NSFC (National Scientific Foundation of China) Project with Tsinghua Univ., 2007

3. Professional Services

• Technical program committee member

 Applied Reconfigurable Computing Symposium (ARC) 2012

 International Conference on Field-Programmable Technology (FPT) 2010

 International Conference on Computational Problem-Solving (ICCP) 2010

• Session Chair

 Design Automation Conference (DAC) 2010

• Reviewer

 IEEE Transactions on Computers

 IEEE Transactions on Computer-Aided-Design of Integrated Circuits and Systems (TCAD)

 IEEE Transactions on Circuits and Systems I/II (TCAS)

 ACM Transactions on Design Automation of Electronic Systems (TODAES).

 IEEE/ACM Design Automation Conference (DAC)

 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)

 IEEE/ACM International Symposium on Field Programmable Gate Array (ISFPGA)

 IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC).

4. Research Interests and Funding

4.1. Research Interests

My research interests include all aspects of field programmable gate arrays (FPGAs), which can be programmed to implement virtually any digital circuit without requiring access to an expensive state-of-the-art chip manufacturing plant. Specifically, I’m investigating the following three lines of FPGA-related research: FPGA-based acceleration algorithms and reconfigurable computing architectures for various high-performance and energy efficient computing problems, FPGA architectures and associated computer-aided design (CAD) tools.

My recent research interests focus on the application of the emerging parallel computing platforms, including state-of-the-art FPGAs, graphic processing units (GPUs) and multi-core CPUs, on massive data processing and data mining. The overall goal of my current research is to develop a systematic methodology and an experimental platform to help people gain better understanding of the feasibilities and tradeoffs of using the emerging reconfigurable computing platforms on data mining and knowledge discovery in the cloud computing era. Particularly, data throughput and energy efficiency will be considered as two primary design/optimization objectives.

In addition, my group is also developing systems to investigate the potential of emerging computation methodologies, e.g., human computation, with the application on data mining.

4.2. Funded Projects

• PI, Startup fund, University of Alberta, CAN$75,000, 2010-2011

• PI, Discovery Grant: Robust Synthesis for Nano-scale FPGAs, funded by Natural Sciences and Engineering Research Council (NSERC) of Canada, CAN$26,000 x 5 years

• PI (Co-PIs: Bruce Cockburn, Jie Han and Vincent Gaudet), Organization of International Workshop on Emerging Circuits and Systems, funded by Canada International Science and Technology Partnerships, CAN$10,000, 2010-2011

• PI (Co-PIs: Osmar Zaiane and Ray Cheung), Acceleration Engine for Graph-based Data Mining Using GPUs, equipment domination (two Tesla C2050) worth USD$7000, 2010-2011

• Co-PI (PI: Osmar Zaiane), Harvesting Human Power for Audio Transcribing By an Online Game, Alberta Ingenuity Centre for Machine Learning (AICML), CAN$8,000, 2010/05-2010/09

5. Publications

5.1. Peer-Reviewed Journal Articles (selected)

J1. Chun Zhang*, Yu Hu, Lingli Wang, Lei He and Jiarong Tong, Accelerating Boolean Matching Using Bloom Filter, IEICE Transactions, Vol.E93-A,No.10,Oct. 2010.

J2. Yu Hu*, Yi-Tao Wang, Adam Stoelting, Yi Zou and Majid Sarrafzadeh, Providing a Cushion for Wireless Healthcare Application Development, IEEE Potentials Magazine, 2010, Jan./Feb. pp. 19-23.

J3. Yu Hu*, Satyaki Das, Steve Trimberger and Lei He, Design and Synthesis of Programmable Logic Block with Mixed LUT and Macro-Gate, IEEE TCAD, 2009, 28(4),pp. 591-595.

J4. Yu Hu*, Victor Shih, Rupak Majumdar and Lei He, Exploiting Symmetries to Speed-Up SAT-Based Boolean Matching for Logic Synthesis of FPGAs, IEEE TCAD, 2008, 27(10), pp.1751-1760.

J5. King Ho Tam, Yu Hu*, Lei He, Tong Jing and Xinyi Zhang, Dual Vdd Buffer Insertion for Power Reduction, IEEE TCAD, 2008, 27(8), pp. 1498-1502.

J6. Yu Hu*, Yan Lin, Lei He and Tim Tuan, Physical Synthesis for FPGA Interconnect Power Reduction by Dual-Vdd Budgeting and Retiming, ACM TODAES, 13, 2 (Apr. 2008), pp. 1-29.

J7. Zhen Cao*, Tong Jing, Jinjun Xiong, Yu Hu, Zhe Feng, Lei He, and Xianlong Hong, Fashion: A Fast and Accurate Solution to Global Routing Problem, IEEE TCAD 2008, 27(4), pp.726-737.

J8. Tong Jing, Yu Hu*, Zhe Feng, Xianlong Hong, Xiaodong Hu and Guiying Yan, A full scale solution to the rectilinear obstacle-avoiding Steiner problem, Elsevier INTEGRATION, the VLSI Journal, 2008, 41(3), pp. 413-425.

J9. Tong Jing, Zhe Feng*, Yu Hu, Xianlong Hong, Xiaodong Hu and Guiying Yan, Lambda-OAT: Lambda-Geometry Obstacle-Avoiding Tree Construction with O (nlogn) Complexity. IEEE TCAD, 26(11), 2007, pp. 2073-2079.

J10. Yu Hu*, Tong Jing, Xianlong Hong, Zhe Feng, Xiaodong Hu, and Guiying Yan, ACO-Steiner: Ant Colony Optimization Based Rectilinear Steiner Minimal Tree Algorithm, Journal of Computer Science & Technology, 2006, 21(1), pp. 147-152.

J11. Yu Hu*, Zhe Feng, Tong Jing, Xianlong Hong, Yang Yang, Ge Yu, Xiaodong Hu, and Guiying Yan. FORst: A 3-Step Heuristic for Obstacle-Avoiding Rectilinear Steiner Minimal Tree Construction. Journal of Information & Computational Science, 2004, 1(3), pp. 107-116.

5.2. Peer-Reviewed Conference Papers

C1. Xiaoyu Shi, Dahua Zeng, Yu Hu*, Osmar Zaiane and Guohui Lin, Accelerating FPGA Design Space Exploration Using Circuit Similarity-Based Placement, FPT, 2010.

C2. Chun Zhang, Yu Hu*, Lingli Wang, Lei He and Jiarong Tong, Engineering a Scalable Boolean Matching Based on EDA SaaS 2.0, ICCAD, 2010

C3. Manu Jose, Yu Hu* and Rupak Majumdar, On Power And Fault-Tolerant Optimization In FPGA Physical Synthesis, ICCAD, 2010.

C4. Manu Jose*, Yu Hu, Rupak Majumdar and Lei He, Rewiring for Robustness, DAC, 2010. (Best paper award nomination, 9 out of 607 submissions)

C5. Samuel Luckenbill*, Ju-Yueh Lee, Yu Hu, Rupak Majumdar, and Lei He, RALF: Reliability Analysis for Logic Faults - An Exact Algorithm and Its Applications, DATE, 2010.

C6. Chun Zhang, Yu Hu*, Lei He, Lingli Wang and Jiarong Tong, Building A Faster Boolean Matcher Using Bloom Filter, FPGA, 2010.

C7. Ju-Yueh Lee, Yu Hu,* Rupak Majumdar, Lei He, and Minming Li, Fault-Tolerant Resynthesis for Dual-Output LUTs, ASP-DAC, 2010.

C8. Lei He and Yu Hu*, Power-Efficient and Fault-Tolerant Circuits and Systems, ASICON, 2009. (Invited paper)

C9. Zhe Feng*, Yu Hu, Lei He and Rupak Majumdar, IPR: In-Place Reconfiguration for FPGA Fault Tolerance, ICCAD, 2009. (Best paper award nomination, 12 out of 438 submissions)

C10. Ju-Yueh Lee*, Yu Hu, Rupak Majumdar, and Lei He, Simultaneous Test Pattern Compaction, Ordering and X-Filling for Testing Power Reduction, IEEE International Symposium on Quality Electronic Design (ISQED), 2009.

C11. Wei Yao*, Yiyu Shi, Lei He, Sudhakar Parmati and Yu Hu, "Worst Case Timing Jitter and Amplitude Noise in Differential Signaling", ISQED, 2009.

C12. Yu Hu*, Zhe Feng, Rupak Majumdar, and Lei He, Robust FPGA Resynthesis Based on Fault Tolerant Boolean Matching, ICCAD, 2008, pp. 706-713. (Best paper award nomination, 9 out of 458 submissions)

C13. Yu Hu*, Victor Shih, Rupak Majumdar, and Lei He, FPGA Area Reduction by Multi-Output Function Based Sequential Resynthesis, DAC, 2008. pp. 24-29.

C14. Yu Hu*, Victor Shih, Rupak Majumdar and Lei He, Exploiting Symmetry in SAT-Based Boolean Matching for Heterogeneous FPGA Technology Mapping, ICCAD, 2007, pp. 350-353.

C15. Yu Hu*, Satyaki Das, Steve Trimberger and Lei He, Design, Synthesis and Evaluation of Heterogeneous FPGA with Mixed LUTs and Macro-Gates, ICCAD, 2007, pp. 188-193.

C16. Hao Yu*, Yu Hu, Chun-Chen Liu and Lei He, Minimal Skew Clock Synthesis Considering Time Variant Temperature Gradient. SRC TechCon Conference, 2007, pp. 70-73.

C17. Hao Yu, Yu Hu, Chun-Chen Liu and Lei He, Minimal Skew Clock Embedding Considering Time Variant Temperature Gradient. ISPD, 2007, pp. 173 - 180.

C18. Yu Hu*, King Ho Tam, Tong Jing and Lei He, Fast Dual-Vdd Buffering Based on Interconnect Prediction and Sampling. IEEE/ACM System Level Interconnect Prediction (SLIP), 2007, pp.95-102.

C19. Yu Hu,* Yan Lin and Lei He, Retiming for High Performance FPGAs Considering Flipflop Constraints and Process Variations. IEEE/ACM International Symposium on Field Programmable Gate Array (ISFPGA), 2007.

C20. Zhen Cao*, Tong Jing, Jinjun Xiong, Yu Hu, Lei He, and Xianlong Hong. DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm. ASP-DAC, 2007, pp. 256 - 261.

C21. Yan Lin, Yu Hu*, Lei He, and Vijay Raghunat. An Efficient Chip-Level Time Slack Allocation Algorithm for Dual-Vdd FPGA Power Reduction. International Symposium on Low Power Electronics and Design (ISLPED), 2006, pp. 168-173.

C22. Yu Hu*, Yan Lin, Lei He and Tim Tuan. Simultaneous Time Slack Budgeting and Retiming for Dual-Vdd FPGA Power Reduction. DAC, 2006, pp. 478-483.

C23. Zhe Feng*, Yu Hu, Tong Jing, Xianlong Hong, Xiaodong Hu and Guiying Yan. An O(nlogn) Algorithm for Obstacle-Avoiding Routing Tree Construction in the λ-Geometry Plane. ISPD, 2006, pp. 48-55.

C24. Zhen Cao*, Tong Jing, Yu Hu, Yiyu Shi, Xianlong Hong, Xiaodong Hu, and Guiying Yan. DraXRouter: Global Routing in X-Architecture with Dynamic Resource Assignment. . IEEE/ACM Asian and South Pacific Design Automation Conference (ASP-DAC) 2006, pp. 618-623.

C25. Yu Hu*, Tong Jing, Xianlong Hong, Xiaodong Hu, and Guiying Yan. A Routing Paradigm with Novel Resources Estimation and Routability Models for X-Architecture Based Physical Design. Embedded Computer Systems: Architectures, MOdeling, and Simulation (SAMOS V) 2005, LNCS 3553, pp. 344-353.

C26. YangYang*, Tong Jing, Xianlong Hong, Yu Hu, Qi Zhu, Xiaodong Hu and Guiying Yan. Via-Aware Global Routing for Good VLSI Manufacturability and High Yield. IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2005, pp. 198-203.

C27. Yu Hu*, Tong Jing, Xianlong Hong, Zhe Feng, Xiaodong Hu, Guiying Yan. An-OARSMan: Obstacle-Avoiding Routing Tree Construction with Good Length Performance, ASPDAC, 2005, pp. 7-12.

5.3. Peer-Reviewed Workshop Papers (W/O Proceedings)

W1. Wenyao Xu, Jia Wang, Yu Hu and Lei He, Retiming for Single Event Transient Mitigation in FPGAs, International Workshop on Logic Synthesis (IWLS), 2009.

W2. Ju-Yueh Lee, Yu Hu, Rupak Majumdar, Lei He, and Minming Li, Fault-Tolerant Resynthesis for Dual-Output LUTs, IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE), 2009.

W3. Yu Hu, Zhe Feng, Rupak Majumdar and Lei He, Templates and Algorithms of Boolean Matching for Fault Tolerance in FPGAs, IWLS, 2008, pp. 200-207.

W4. Yu Hu, Victor Shih, Rupak Majumdar, and Lei He, Mapping and Resynthesis for LUT-based FPGAs with an Efficient SAT-Based Boolean Matching, IWLS, 2008, pp. 154-156. (Best Contribution Award of IEEE Programming Challenge at IWLS)

5.4. Patents

P1. A method for obstacle-avoiding routing tree construction with good wire-length performance. (Chinese patent pending 200410090885.5. published on 2005/04/06), By Xianlong Hong, Tong Jing, Yu Hu, Zhe Feng, and Yang Yang.

P2. A method for obstacle-avoiding rectilinear Steiner minimum tree construction. (Chinese patent 200410069118.6, granted), By Xianlong Hong, Tong Jing, Yu Hu, Zhe Feng, and Yang Yang.

P3. A method for timing-driven global routing considering coupling effects. (Chinese patent 03124095.X, granted) By Xianlong Hong, Tong Jing, Jingyu Xu, Ling Zhang, and Yu Hu.

P4. A method for standard cell global routing considering crosstalk reduction. (Chinese patent 02156622.4, granted) By Xianlong Hong, Tong Jing, Jingyu Xu, Ling Zhang, and Yu Hu.

5.5. Invited Talks

T1. Yu Hu, Engaging FPGA Research in Cloud Computing Era, International Workshop on Emerging Circuits and Systems, 08/05/2010, Hefei, China.

T2. Yu Hu, Robust Logic Synthesis and Its Application on Cyber Physical Systems, International Workshop on Emerging Circuits and Systems, 07/07/2009, Shanghai, China.

T3. Yu Hu, Fault-Tolerant Synthesis for FPGAs, 11/05/2008, Actel Corp.

T4. Yu Hu, SAT-Based Boolean Matching and Macro-Gate-Based Heterogeneous FPGAs, 11/04/2007, Actel Corp.