I SILICON AND TRANSISTORS
2 Semiconductor Device Physics - J ¨org Kramer 7
2.1 Crystal Structure 7
2.2 Energy Band Diagrams 9
2.3 Carrier Concentrations at Thermal Equilibrium 13
2.4 Impurity Doping 15
2.5 Current Densities 19
2.6 p-n Junction Diode 24
2.7 The Metal-Insulator-Semiconductor Structure 35
3 MOSFET Characteristics - Shih-Chii Liu and Bradley
A. Minch 47
3.1 MOSFET Structure 48
3.2 Current–Voltage Characteristics of an nFET 52
3.3 Current–Voltage Characteristics of a pFET 70
3.4 Small-Signal Model at Low Frequencies 71
3.5 Second-Order Effects 75
3.6 Noise and Transistor Matching 80
3.7 Appendices 81
4 Floating-Gate MOSFETs - Chris Diorio 93
4.1 Floating-Gate MOSFETs 93
4.2 Synapse Transistors 98
4.3 Silicon Learning Arrays 107
4.4 Appendices 116
Contents
Authors and Contributors xiii
Acknowledgments xv
Preface xvii
Foreword xix
1 Introduction 1
I SILICON AND TRANSISTORS
2 Semiconductor Device Physics - J ¨org Kramer 7
2.1 Crystal Structure 7
2.2 Energy Band Diagrams 9
2.3 Carrier Concentrations at Thermal Equilibrium 13
2.4 Impurity Doping 15
2.5 Current Densities 19
2.6 p-n Junction Diode 24
2.7 The Metal-Insulator-Semiconductor Structure 35
3 MOSFET Characteristics - Shih-Chii Liu and Bradley
A. Minch 47
3.1 MOSFET Structure 48
3.2 Current–Voltage Characteristics of an nFET 52
3.3 Current–Voltage Characteristics of a pFET 70
3.4 Small-Signal Model at Low Frequencies 71
3.5 Second-Order Effects 75
3.6 Noise and Transistor Matching 80
3.7 Appendices 81
4 Floating-Gate MOSFETs - Chris Diorio 93
4.1 Floating-Gate MOSFETs 93
4.2 Synapse Transistors 98
4.3 Silicon Learning Arrays 107
4.4 Appendices 116
viii Contents
II STATICS
5 Basic Static Circuits - J¨org Kramer 123
5.1 Single-Transistor Circuits 124
5.2 Two-Transistor Circuits 127
5.3 Differential Pair and Transconductance Amplifier 133
5.4 Unity-Gain Follower 142
6 Current-Mode Circuits - Giacomo Indiveri and Tobias
Delbr¨uck 145
6.1 The Current Conveyor 145
6.2 The Current Normalizer 148
6.3 Winner-Take-All Circuits 150
6.4 Resistive Networks 164
6.5 Current Correlator and Bump Circuit 168
7 Analysis and Synthesis of Static Translinear Circuits
- Bradley A. Minch 177
7.1 The Ideal Translinear Element 179
7.2 Translinear Signal Representations 181
7.3 The Translinear Principle 183
7.4 ABC’s of Translinear-Loop–Circuit Synthesis 195
7.5 The Multiple-Input Translinear Element 202
7.6 Multiple-Input Translinear Element Networks 205
7.7 Analysis of MITE Networks 210
7.8 ABC’s of MITE-Network Synthesis 216
III DYNAMICS
8 Linear Systems Theory - Giacomo Indiveri 231
8.1 Linear Shift-Invariant Systems 231
8.2 Convolution 234
Contents ix
8.3 Impulses 236
8.4 Impulse Response of a System 237
8.5 Resistor-Capacitor Circuits 240
8.6 Higher Order Equations 241
8.7 The Heaviside-Laplace Transform 243
8.8 Linear System’s Transfer Function 244
8.9 The Resistor-Capacitor Circuit (A Second Look) 246
8.10 Low-Pass, High-Pass, and Band-Pass Filters 249
9 Integrator-Differentiator Circuits - Giacomo Indiveri
and J¨org Kramer 251
9.1 The Follower-Integrator 252
9.2 The Current-Mirror Integrator 256
9.3 The Capacitor 261
9.4 The Follower-Differentiator Circuit 263
9.5 The diff1 and diff2 Circuits 264
9.6 Hysteretic Differentiators 270
10 Photosensors - J ¨org Kramer and Tobias Delbr ¨uck 275
10.1 Photodiode 275
10.2 Phototransistor 283
10.3 Photogate 284
10.4 Logarithmic Photosensors 286
10.5 Imaging Arrays 299
10.6 Limitations Imposed by Dark Current on Photosensing 307
IV SPECIAL TOPICS
11 Noise in MOS Transistors and Resistors - Rahul
Sarpeshkar, Tobias Delbr ¨uck, Carver Mead, and
Shih-Chii Liu 313
x Contents
11.1 Noise Definition 313
11.2 Noise in Subthreshold MOSFETs 317
11.3 Shot Noise versus Thermal Noise 325
11.4 The Equipartition Theorem and Noise Calculations 328
11.5 Noise Examples 333
12 Layout Masks and Design Techniques - Eric Vittoz,
Shih-Chii Liu, and J ¨org Kramer 341
12.1 Mask Layout for CMOS Fabrication 341
12.2 Layout Techniques for Better Performance 346
12.3 Short List of Matching Techniques 351
12.4 Parasitic Effects 353
12.5 Latchup 355
12.6 Substrate Coupling 356
12.7 Device Matching Measurements 359
13 A Millennium Silicon Process Technology - Albert
Bergemont, Tobias Delbr ¨uck, and Shih-Chii Liu 361
13.1 A typical 0.25 m CMOS Process Flow 361
13.2 Scaling Limits for Conventional Planar CMOS
Architectures 373
13.3 Conclusions and Guidelines for New Generations 382
14 Scaling of MOS Technology to Submicrometer
Feature Sizes - Carver Mead 385
14.1 Scaling Approach 386
14.2 Threshold Scaling 394
14.3 Device Characteristics 395
14.4 System Properties 402
14.5 Conclusions 402
Contents xi
Appendix A:
Units and symbols 407
References 415
Index 429
